Fault-tolerant ATM switch structure design and input-queueing switch performance analysis

by Rui-Feng Liao

Publisher: National Library of Canada in Ottawa

Written in English
Published: Downloads: 753
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Edition Notes

Thesis (M.A.Sc.)--University of Toronto, 1993.

SeriesCanadian theses = Thèses canadiennes
The Physical Object
Pagination2 microfiches : negative.
ID Numbers
Open LibraryOL15136246M
ISBN 100315871571

The most famous pattern book is Design Patterns Elements of Reusable Object Oriented Design by Erich Gamma, Richard Helm, Ralph Johnson, and John Vlissides, the so-called Gang of Four [GHJ+95]. Many other books have followed, covering topics ranging from business process analysis to real-time programming to programming language specific techniques. / high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, . "Analysis of an ATM multiplexer with prioritized service" (with S. Montagna, R. Paglino, and A. Puglisi), in Proc. 5th Int'l Workshop on Performance Modelling and Evaluation of ATM .   However smart-design considerations [20, 21] and dedicated control strategies [22, 23] were applied to increase the fault-tolerant potential of the machine. In order to achieve a more increased level of fault tolerance, a nine-phase PMSM is proposed supplied from a special electronic converter able to overcome and compensate the occurred fault.

  Layer 2 Access Design Recommendations. Proper access layer design starts with assigning a single IP subnet per virtual LAN (VLAN). Typically, a VLAN should not span multiple wiring closet switches; that is, a VLAN should have presence in one and only one access layer switch (see Figure ).This practice eliminates topological loops at Layer 2, thus avoiding temporary flow .   Abstract. We study the problem of designing fault-tolerant virtual path layouts for an ATM network which is a biconnected network of n processors in the surviving route graph model. The surviving route graph for a graph G, a routing p and a set of faults F is a directed graph consisting of nonfaulty nodes with a directed edge from a node x to a node y iff there are no faults on the route from. ATM (asynchronous transfer mode) is an internationally standardized connection-oriented packet switching protocol designed to support a wide variety of data, voice, and video services in public and private broadband networks (1,2). ATM networks generally consist of ATM switches interconnected by high-speed transmission links. 7,8,9,10,11) and advances in the analysis and control of hybrid process systems leading to the development of a systematic framework for the integration of feedback and supervisory control,13 A hybrid systems framework provides a natural setting for the analysis and design of fault-tolerant control.

Busy period analysis for an ATM switching element output line. Configuring Fault-Tolerant Servers for Best Performance. queue with vacation time and exhaustive service discipline. Entropy and the timing capacity of discrete queues. Throughput analysis of a fault-tolerant optical switch. When a multistage switch becomes nonblocking? The multistage switch with k=2n-1 is nonblocking The number of crosspoints required in a three stage switch is the sum of the following components N/n ×nk +k ×(N/n)2+N/n ×nk=2Nk+k(N/n)2 EE Telecom. Switching & Transmission Prof. Murat Torlak. Figure ATM header structure for User-Network Interface(UNI) Figure ATM header structure for Network-NetworkInterface (NNI) Figure Relation between virtual channel, virtual path and physical path 7. Whether you are a communications engineer working in system architecture and waveform design, an RF engineer working on noise and linearity budget and line-up analysis, a DSP engineer working on algorithm development, or an analog or digital design engineer designing circuits for wireless transceivers, this book is your one-stop reference and.

Fault-tolerant ATM switch structure design and input-queueing switch performance analysis by Rui-Feng Liao Download PDF EPUB FB2

Segkhoonthod S, Sinclair MC. Re-routing analysis of a fault-tolerant ATM switch based on a parallel architecture. Third IFIP Workshop on Performance Modelling and Evaluation of ATM Networks, likely, ; 73/1–73/ Google ScholarAuthor: S.

Segkhoonthod, M. Sinclair. Abstract -Asynchronous Transfer Mode (ATM) switching is not defined in the ATM standards, but a lot of research has been done to explore various ATM switch design design has its own merits and drawbacks, in terms of throughput, delay, scalability, buffer sharing and fault tolerance.

By examining the features of the basic switch designs, several conclusions can be inferred. The objective of this study is the design of a packet switch with a minimum cost and hardware complexity.

Various MIN structures exist to improve the performance. This paper in-vestigates the. CiteSeerX - Document Details (Isaac Councill, Lee Giles, Pradeep Teregowda): In this paper, we propose a new method to build a fault tolerant ATM switch.

Using this method, we can build an ATM switch which has two disjoint paths between each input/ output pair. The key component in the proposed switch is a 2 ¥ 2 FTSE (Fault Tolerant Switching Element), which can be used as the basic building.

The performance analysis of the fault-tolerant operation is discussed in Section 4. Implementation issues The queue management and the virtual FIFO mechanism of the multichannel switch have been built as a part of the 16 X 16 multicast ATM switch in Carnegie Mellon University [3].Cited by: 2.

This paper introduces and studies the performance of an N×N space-division, single-stage ATM switch with dual input-queueing. Each input port has two separate FIFO queues, an “odd” and an. CiteSeerX - Document Details (Isaac Councill, Lee Giles, Pradeep Teregowda): This paper presents a fault-tolerant ATM switch which adapts the idea of using MINs in parallel.

It has a distribution network to distribute incoming packets to several routing networks arranged in parallel. Consequently, the IPC is simply required to submit packets to the distribution network. Grid-based ATM Switch Architecture: a new fault-tolerant space-division switch fabric architecture model for the design and analysis of dilated banyan switches.

on the same time. the FAN. A high-performance fault-tolerant ATM switch (B-tree) is proposed. This switch embeds multiple baseline networks tightly to improve the fault tolerance and throughput of conventional multistage.

CiteSeerX - Document Details (Isaac Councill, Lee Giles, Pradeep Teregowda): this paper, we extend the work in [4] by taking into account the presence of a single fault in various parts of the switch. 2 Switch Architecture and Operation. this method, we can build an ATM switch which has two disjoint paths between each input/ output pair.

The key component in the proposed switch is a 2 2 FTSE (Fault Tolerant Switching Element), which can be used as the basic building block for high speed ATM switches.

The design of the FTSE-based fault tolerant ATM switch is based on a multi. N.K. Sharma, RU. Tagle / Performance Evaluation 34 () 93 Fig.

An N = 8 sorting network. To design a fault-tolerant ATM switch based on Batcher banyan configuration, both the sorting and routing networks must be fault-tolerant. Many fault-tolerant routing networks have been proposed [8,10,11,15]. other switch networks, in particular, to a fully-connected network of switches.

The structure of the paper follows closely the contributions listed above. In Section 2 we formally define the problem of creating fault-tolerant switched networks. We then, in Section 3, give our primary construction based. Kolias and L. Kleinrock, "The Odd-Even Input-Queueing ATM Switch: Performance Evaluation," in Proceedings of ICC'96, June, pp.

– [PDF] [BibTex] L. Kleinrock, "Nomadic Computing," in Information Network and Data Communication, IFIP/ICCC International Conference on Information Network and Data Communication, Trondheim.

Fault tolerance is the property that enables a system to continue operating properly in the event of the failure of (or one or more faults within) some of its components. If its operating quality decreases at all, the decrease is proportional to the severity of the failure, as compared to a naively designed system, in which even a small failure can cause total breakdown.

Each of the fault-tolerant network design methods presented (channel bonding drivers, Layer 2 methods, and Layer 3 methods) are best used together to achieve maximum availability. The following shows an example of all methods combined into a single network configuration.

FIGURE 4 Fault-Tolerant Network Combining All Design Methods. In this structure (Figure 1 again), when an analog input signal exceeds the gate voltage by the threshold value, the output stage conducts this fault right through the switch to the output.

Also, if the power supplies are off while signals are present at the input (that is, there is 0V on the gates of N1 and P1), any signal exceeding the. In this paper, we propose a new architecture for multicast ATM switches with fault tolerant capability based on the Clos–Knockout switch.

In the new architecture, each stage has one more redundant switch module. If one switch module is faulty, the redundant module would replace the faulty one. 4. Design of fault-tolerance method for FCBBC. When a short-circuit fault occurs on one of the power switches in the FCBBC, the converter can transition into a fault-tolerant operation mode.

After the short fault is identified and located using the technique described above, microprocessor will turn off the corresponding switch T n.

The FCBBC. Consequently, if an SN fails, system performance is bound to deteriorate or, in the worst case, the system may collapse totally. To limit these troubling consequences, the SN has to be fault tolerant [11]. Loosely defined, a fault tolerant SN is a SN that can still work in the presence of faults.

as a Fault tolerant structural design in [13]. Commault et al. and T. Boukhobza et al. developed structural methods using graph theory in [14], [15].

Many more papers review monitoring aspect of LPS in order to real time operation and scheduling [23]-[27]. Fault Tolerant Control of Power Systems in presence of Sensor Failure. An asynchronous mode transfer (ATM) switch conducting switching based upon the calculation of weights for entries corresponding to cells in an input queue to achieve a high throughput rate which avoids head of line blocking.

The switch includes a cell scheduler driven by the iterative resolution of a traffic matrix formed by highest priority entries for each of a plurality of output ports. fault tolerant switch architectures, also employing redundancy, were presented and an alyzed. In [10] a new non-Banyan-based switch fabric architecture, the “Grid-based ATM Switch Archi-tecture” (GASA), was presented.

In the same paper performance issues (performance analytical model and simulation results) were presented and studied. ance is essential to ATM systems, few fault-tolerant switch-ing networks have been proposed for ATM.

Adam and Siegel proposed the extra stage cube (ESC) network [7] which adds an extra stage to the input side of the cube network. Although the ESC network is robust in the presence of multiple faults, it requires extra logic and extra computation.

The objective of creating a fault-tolerant system is to prevent disruptions arising from a single point of failure, ensuring the high availability and business continuity of mission-critical applications or systems. Fault-tolerant systems use backup components that automatically take the place of failed components, ensuring no loss of service.

Design and performance analysis of load-distributing fault-tolerant network IEEE Transactions on Computers, Vol. 45, No.

5 Delay performance of some scheduling strategies in an input queuing ATM switch with multiclass bursty traffic.

This paper presents the architecture of a very high-speed VLSI packet switch and its performance. The switch, called PRIZMA, is suited for broadband t. In this paper we quantitatively evaluate three iterative algorithms for scheduling cells in a high-bandwidth input-queued ATM switch.

In particular, we compare the performance of an algorithm described previously – parallel iterative matching (PIM) – with two new algorithms: iterative round-robin matching with slip (iSLIP) and iterative least-recently used (iLRU). provide satisfactory performance, has led to fault tolerant control being an active area of research.

This thesis addresses this issue with the design of two fault tolerant nonlinear Structured Adaptive Model Inversion control schemes for systems with fixed magnitude discrete controls. Both methods can be used for proportional as well as.

The description is modular and reflects the structure of the design. The major sections are management procedures, Y.C. Jenq, "Performance analysis of a packet switch based on a single-buffered banyan network," IEEE Journal of Selected Areas in Communications, vol.

SAC-3, no. 6, pp.Dec. [8] ATM switch design switch. Fault-tolerant computing is the art and science of building computing systems that switch out a faulty module, switch in a spare, and instigate those software actions (rollback, initialization, retry, restart) necessary to restore especially in high performance scalable systems in which the amount of .He is currently involved in developing routing and admission control strategies for broadband ATM networks, and in the design and analysis of multicast switch architectures.

Prof. Naraghi-Pour's other areas of interest include data compression, coding theory, modulation, information theory and .Keywords: ATM, switch architecture, performance analysis, tree-based switches.

ii Contents A B S T R A C T ii List of Tables v List of Figures vi Chapter 1 Introduction 1 ATM Evolution 2 Abstract Model of an ATM Switch 4 Requirements of the Ideal ATM Switch 7 Thesis Outline 11 Chapter 2 Topologies and Queueing Design of ATM.